The present invention relates to an output circuit for a semiconductor integrated circuit, and in particular, to an output circuit for controlling the inclination of a signal waveform (a falling or rising time) upon a rise or fall in an output signal from a CMOS circuit, the output circuit being connected, for example, to an I.sup.2 C-bus external to an integrated circuit.
A circuit for controlling the inclination of a signal waveform upon a fall or rise in an output signal from an output circuit for a semiconductor integrated circuit (LSI), that is, a circuit for controlling a rising or falling time is important as a technique for restraining switching noise. An example of such a circuit is disclosed in "The I2 C-bus specifications version 2.0, December 1998", Philips Semiconductors, page 41, FIG. 41.
This document defines a FAST mode to provide a rising time between a predetermined minimum and maximum values with respect to a wide range of load capacitance values (between 10 pF and 400 pF). This document recommends this mode as a "slope controlled output stage in CMOS technology".
A circuit 200 enclosed by the broken line shown in FIG. 1 shows the configuration of a conventional output circuit recommended in the above document.
In this output circuit 200, a P-channel MOS transistor (hereafter referred to as a "PMOS transistor") P10, a resistance element R10, and an N-channel MOS transistor (hereafter referred to as an "NMOS transistor") N10 are connected in series between a power potential (VDD) node and a ground potential (GND) node to constitute an output buffer circuit. Gates of the PMOS transistor P10 and the NMOS transistor N10 are connected to an input node SIN. A node K (an output node of the output buffer circuit) having the resistance element R10 and the NMOS transistor N10 connected thereto is connected to an I/O node SIO via a capacitance element C10. An NMOS transistor N20 is connected between the I/O node SIO and the GND node, with its gate connected to the node
Reference numeral RP denotes a resistance element for pulling up an external bus (I.sup.2 C-bus) connected to the I/O node SIO of the LSI, to a high potential (in this example, VDD), and reference numeral CL denotes capacitive load on the I/O node SIO. The I/O node SIO also has an input circuit (not shown) in the LSI connected thereto.
FIG. 2 shows an operational waveform from the output circuit in FIG. 1.
When the input node SIN is at the potential VDD, the NMOS transistor N10 is turned on while the PMOS transistor P10 is turned off, thereby setting the node K at the GND. In addition, the NMOS transistor N20 is turned off and the I/O node SIO is pulled up to the VDD by means of the resistance element RP.
When the potential of the input node SIN changes to the GND, the NMOS transistor N10 is turned off while the PMOS transistor P10 is turned on, thereby raising the node K to the VDD. At this point, the VDD node charges the load capacitance (partly consisting of the capacitance element C10) of the node K via the resistance element R10, thereby reducing a speed at which the potential of the node K rises.
In response to the rise in the potential of the node K, the NMOS transistor N20 is turned on to lower the potential of the I/O node SIO from the VDD to the GND. In this case, in response to the fall in the potential of the I/O node SIO, the capacitance element C10 pulls the node K to the GND, thereby further diminishing the rising speed of the potential of the node K.
Consequently, a speed further decreases at which an on resistance of the NMOS transistor N20 decreases in response to the rise in the potential of the node K, thereby lowering the drop speed of the potential of the I/O node SIO. The potential of the I/O node SIO finally reaches a value obtained by a divided resistance including the on resistance of the NMOS transistor N20, to which the gate voltage that has reached the VDD is applied, and the resistance element RP (this value is hereafter referred to as a "divided voltage value").
On the contrary, when the potential of the input node SIN changes from the GND to the VDD, the PMOS transistor P10 is turned off while the NMOS transistor N10 is turned on, thereby lowering the node K to the GND. At this point, the load capacitance (partly consisting of the capacitance element C10) of the node K is discharged to reduce a speed at which the potential of the node K falls.
Then, in response to the fall in the potential of the node K, the on resistance of the NMOS transistor N20 increases to raise the potential of the I/O node SIO from the divided voltage value to the VDD. In this case, in response to the rise in the potential of the I/O node SIO, the capacitance element C10 pulls the node K to the VDD, thereby further diminishing the falling speed of the potential of the node K.
Consequently, the speed further decreases at which the on resistance of the NMOS transistor N20 decreases in response to the fall in the potential of the node K, thereby lowering the rising speed of the potential of the I/O node SIO. The potential of the I/O node SIO finally reaches the VDD.
Next, problems of the above described conventional technique will be explained.
When the potential of the input node SIN changes from the GND to the VDD, the capacitance element C10 diminishes the rising speed of the potential of the node K. Accordingly, a large amount of time is required until the NMOS transistor N20 is turned off, and a DC current flows from the external VDD to the GND through the pull-up resistance element RP and the NMOS transistor N20. This DC current is unwanted and should be eliminated.
Alternatively, if, for example, the NMOS transistor N20, which is part of the output circuit 200, is an element formed using a device technology that allows the NMOS transistor N20 to be used in a 3.3-V system (system for operation under a power voltage of 3.3 V.+-.0.3 V) LSI and the resistance element RP pulls the potential up to 5 V, this potential of 5 V is applied between a drain and source of the NMOS transistor N20 and between a drain and gate thereof.
In addition, if the capacitance element C10 is formed using a gate oxide film in a MOS transistor that is a 3.3-V device, electric fields resulting from a potential difference of 5 V are applied to the gate oxide film.
As described above, if the NMOS transistor N20 or the capacitance element C10, which is part of the output circuit 200, is a 3.3-V device that can withstand a voltage of about 4.5 V and the resistance element RP pulls the potential up to 5 V as described above, the NMOS transistor N20 or the capacitance element C10 will be unreliable. No measures for solving such a problem are disclosed in the above described document.
As described above, the output circuit for the conventional LSI is disadvantageous in that the capacitance element connected between the output terminal of the output buffer circuit and I/O terminal may cause an unwanted DC current to flow from the pull-up resistance element of the external bus to the transistor connected to the output terminal. In addition, if the pull-up potential of the external bus is higher than the withstand voltage of the transistor connected to the output terminal, the transistor will be unreliable.